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HL14203
HL14203
LCD Driver IC
Preliminary
2Q. 1999
Hyundai Electronics Industries System IC Division
1
Preliminary
HL14203
Contents
1. General Description 2. Features 3. Block Diagram 4. Pin Diagram 5. Pin Description 6. Serial I/O Data Format 7. Registers 8. Key Scan Function 9. LCD Function 10. Power On Reset 11. Power Down Mode 12. Oscillator Port 13. Electrical Characteristics 14. Application
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Preliminary
HL14203
1. General Description The HL14203 is 1/3 duty LCD display driver. It can drive directly maximum 126 segments. Also it has four general purpose output ports and a key scan function that accepts input from up to 30 keys. 2. Features * LCD display ..................................... 42 segments x 3 commons 1/3 duty - 1/2 bias 1/3 duty - 1/3 bias Key scan ............................................ Maximum 30 keys Input 5 pins, Output 6 pins Power down mode ............................. Sleep mode and all segments off mode Port Output .................................................. 4 pins ( Including the LCD segment port ) Serial I/O .............................................. Data transfer and receive Power on reset ..................................... Supply voltage detection ( SVD ) RC oscillator Package ............................................... 64QFP Package Dimensions
64QFP (14x14)
17.2
* * *
* * * *
64QFP (10x10)
0.5
0.1 1.7max 0.5 1.25
(1.6)
14.0 1.0 48 49 1.0 0.8 33 32
(1.6) 1.0 0.15 48 49
12.0 10.0 32 33
0.15
17.2
14.0
0.8
12.0 10.0
64 1 1.0 0.35
17 16 2.7 0.1
64
1 0.18
17 16
Unit : mm
Unit : mm
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Preliminary
1.25
0.5
HL14203
3. Block Diagram
KS2 / SEG42 KS1 / SEG41 SEG40
SEG5 SEG4 / P4
COMMOM DRIVER
COM3 COM2 COM1
SEGMENT DRIVER LCD DISPLAY & CONTROL REGISTER RESET
VCL1 VCL2 VDD VSS
LCD BIAS SVD
SEG1 / P1
OSC
CLOCK GENERATOR TEST CONTROL
SERIAL I/O CLOCK KEY SCAN
SI SO SCK CE
TEST
KS6 KS5 KS4 KS3 KS2 KS1
KIN5 KIN4 KIN3 KIN2 KIN1
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Preliminary
HL14203
4. Pin Diagram
KS6 KIN1 KIN2 KIN3 KIN4 KIN5 TEST VDD VCL1 VCL2 VSS OSC SO CE SCK SI
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
KS5 KS4 KS3 KS2 / SEG42 KS1 / SEG41 COM3 COM2 COM1 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33
HL14203
SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17
SEG1 / P1 SEG2 / P2 SEG3 / P3 SEG4 / P4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
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Preliminary
HL14203
5. Pin Description
PIN Name SEG[42:1] COM [3:1] VCL[2:1] OSC KS[6:1] KIN[5:1] CE SCK SO SI TEST P[4:1] VDD VSS I/O O O I I/O O I I I O I I O I I Pin Number 42 3 2 1 6 5 1 1 1 1 1 4 1 1 Contents LCD SEG Pins share P1,P2,P3 and P4 LCD Common Pins LCD Bias Pins Oscillator Input Pin Key Scan Output Pins Key Scan Input Pins Serial I/O Control Pin Serial I/O Clock Pin Serial I/O Data Output Pin Serial I/O Data Input Pin Test Pin. "1" Test mode , "0" Normal Mode Output Port share SEG[4:1] Power Supply Pin Ground Pin
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Preliminary
HL14203
6. Serial I/O Data Format 1) Writing Mode
i )SCK is stopped at the low level
CE SCK SI SO
XX 0 A0 1 A1 0 A2 0 A3 0 A4 0 A5 1 A6 0 A7 D1 D2 D3 D41 D42 0 0 0 0 S0 S1 K0 K1 P0 P1 SC DR 0 DD 0
Display data
Control data
CE SCK SI SO
XX 0 A0 1 A1 0 A2 0 A3 0 A4 0 A5 1 A6 0 A7 D43 D44 D45 Display data D83 D84 0 0 0 0 0 0 0 0 0 0 0 0 0 DD 1
Fixed data
CE SCK SI SO
XX 0 A0 1 A1 0 A2 0 A3 0 A4 0 A5 1 A6 0 A7 D85 D86 D87 Display data
D125 D126
0
0
0
0
0
0
0
0
0
0
0
0
1 DD
0
Fixed data
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Preliminary
HL14203
ii )SCK is stopped at the high level
CE SCK SI SO
XX 0 A0 1 A1 0 A2 0 A3 0 A4 0 A5 1 A6 0 A7 D1 D2 D3 Display data D41 D42 0 0 0 0 S0 S1 K0 K1 P0 P1 SC DR 0 DD 0
Control data
CE SCK SI SO
XX 0 A0 1 A1 0 A2 0 A3 0 A4 0 A5 1 A6 0 A7 D43 D44 D45 Display data D83 D84 0 0 0 0 S0 S1 K0 K1 P0 P1 SC DR 0 DD 1
Fixed data
CE SCK SI SO
XX 0 A0 1 A1 0 A2 0 A3 0 A4 0 A5 1 A6 0 A7 D85 D86 D87 Display data
D125 D126
0
0
0
0
S0
S1
K0
K1
P0
P1
SC DR
1 DD
0
Fixed data
A7~A0 : 42H address D126~D1 : Data of LCD display registers S0, S1 : Sleep control data K0, K1 : Key scan output / Segment output selection data P0, P1 : Segment output / general-purpose output port selection data SC : Segment on / off control data DR : 1/2 bias or 1/3 bias drive selection data
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Preliminary
HL14203
2) Reading Mode
i ) SCK is stopped at the low level
CE SCK SI SO
XX 1 1 0 0 0 0 1 0 XX
A0 A1 A2 A3 A4 A5 A6 A7 XX K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12
Output data X : don't care
K29 K30
SA
XX
ii ) SCK is stopped at the high level
CE SCK SI SO
XX 1 1 0 0 0 0 1 0 XX
A0 A1 A2 A3 A4 A5 A6 A7
XX K1
K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12
Output data
K29
K30
SA XX
X : don't care
A7 ~ A0 : 43H address K30 ~ K1 : Key data SA : Sleep acknowledge
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Preliminary
HL14203
7. Registers 1) Display Registers
Output Pin SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42
COM1 D1 D4 D7 D10 D13 D16 D19 D22 D25 D28 D31 D34 D37 D40 D43 D46 D49 D52 D55 D58 D61 D64 D67 D70 D73 D76 D79 D82 D85 D88 D91 D94 D97 D100 D103 D106 D109 D112 D115 D118 D121 D124
COM2 D2 D5 D8 D11 D14 D17 D20 D23 D26 D29 D32 D35 D38 D41 D44 D47 D50 D53 D56 D59 D62 D65 D68 D71 D74 D77 D80 D83 D86 D89 D92 D95 D98 D101 D104 D107 D110 D113 D116 D119 D122 D125
COM3 D3 D6 D9 D12 D15 D18 D21 D24 D27 D30 D33 D36 D39 D42 D45 D48 D51 D54 D57 D60 D63 D66 D69 D72 D75 D78 D81 D84 D87 D90 D93 D96 D99 D102 D105 D108 D111 D114 D117 D120 D123 D126
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Preliminary
HL14203
2) Control Registers Bias Selection Register
DR 0 1 Bias Selection 1/3 Bias 1/2 Bias
Key Scan / Segment output Selection Register
Control Data K0 K1 0 0 0 1 1 X Output Pin Status Maximum number of Input Pins KS1/SEG41 KS2/SEG42 KS1 KS2 30 SEG41 KS2 25 SEG41 SEG42 20
Port Mode Register
Control Data P0 P1 0 0 0 1 1 0 1 1 SEG1/ P1 SEG1 P1 P1 P1 Output Pin Status SEG2/ P2 SEG3/ P3 SEG2 SEG3 P2 SEG3 P2 P3 P2 P3 SEG4/ P4 SEG4 SEG4 SEG4 P4
Port Data Register
Output Pin SEG1 / P1 SEG2 / P2 SEG3 / P3 SEG4 / P4 Port Data Register D1 D4 D7 D10
Sleep Mode Control Register
Control Data Output Pin Status OSC SEG / COMMON Mode Output Oscillator S0 S1 KS1 KS2 KS3 KS4 KS5 0 0 Normal Operating Operating H H H H H 0 1 Sleep Stopped L L L L L L 1 0 Sleep Stopped L L L L L H 1 1 Sleep Stopped L H H H H H KS6 H H H H
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Preliminary
HL14203
Display On/Off Control Register
Control Data SC 0 1 Display Status SEG1 ~ SEG42 On Off
Key Scan Data & Sleep Acknowledge Read
ADDRESS 43H
KIN1 K1 K6 K11 K16 K21 K26
Read Data K1 ~ K30, SA
KIN1 K2 K7 K12 K17 K22 K27 KIN1 K3 K8 K13 K18 K23 K28 KIN1 K4 K9 K14 K19 K24 K29 KIN1 K5 K10 K15 K20 K25 K30
KS1 / SEG41 KS2 / SEG42 KS3 KS4 KS5 KS6
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Preliminary
HL14203
8. Key Scan Function 1) Key Scan Timing The key scan period is 384T. The HL14203 scans the key twice and determines that a key has been pressed when the key data agrees. It outputs a key data read request 800T after starting a key scan. If the key data does not agree and a key was pressed at that point, it scans the key again.Thus the HL14203 cannot detect a key press shorter than 800T.
KS1 KS2 KS3 KS4 KS5 KS6
*) *) *) *) *) *)
1 2 3 4 5 6
1 2 3 4 5 6 768T
*) *) *) *) *) *)
Key on
*) In sleep mode the high / low state of these pins is determined by the S0,S1 bits in the control data. Key scan output signals are not output from pins that are set low.
2) In normal mode * The pins KS1 to KS6 are set high. * When a key is pressed a key scan is started and the keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set. * If a key is pressed for longer than 800T ( where T=1/fosc ) the HL14203 outputs a key data read request (a low level on SO pin) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, SO will be set high. * After the controller reads the key data, the key data read requests is cleared ( SO pin is set high ) and the HL14203 performs another key scan. Also note that SO pin, being an open-drain output, requires a pull-up resistor. 13 Preliminary
HL14203
Key input 1
Key input 2
Key Scan
800T
800T
800T
CE
Write address Write address Read address Write address Read address Read address
SI SO
Key data read Key data read request Key data read Key data read request Key data read Key data read request
3) In sleep mode * The pins KS1 to KS6 are set to high or low by the S0 and S1 bits in the sleep mode control register. * If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, the oscillator on the OSC pin is started and a key scan is performed. Keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set. * If a key is pressed for longer than 800T ( where T=1/fosc ) the HL14203 outputs a key data read request (a low level on SO) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, SO will be set high. * After the controller reads the key data, the key data read request is cleared ( SO is set high ) and the HL14203 performs another key scan. However this does not clear sleep mode. Also note that SO, being an open-drain output, requires a pull-up resistor ( between 1 and 10 K). * Sleep mode key scan example Example : S0 = 0, S1 = 1 ( sleep with only KS6 high )
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Preliminary
HL14203
"L" KS1 "L" KS2 "L" KS3 "L" KS4 "L" KS5 "H" KS6 *) KIN1 KIN2 KIN3 KIN4 KIN5
*) These diodes are required to reliable recognize multiple key presses on the KS6 line when sleep mode state with only KS6 high, as in the above example. That is, these diodes prevent incorrect operation due to sneak currents in the KS6 key scan output signal when keys on the KS1 to KS5 lines are pressed at the same time. When any one of these keys is pressed, the oscillator on the OSC pin is started and the keys are scanned.
Key input (KS6 line) Key Scan
800T
CE
Write address Write address Read address
800T
Write address
Read address
SI SO
Key data read Key data read request Key data read Key data read request
Multiple Key Presses Although the HL14203 is capable of key scanning without inserting diodes for dual key presses, triple key presses on the KIN1 to KIN5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other than these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be inserted in series with each key. Application that do not recognize multiple key presses of threes or keys should check the key data for three or more 1 bits and ignore such data.
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Preliminary
HL14203
9. LCD Display Function
1) 1/3 Duty 1/2 Bias Waveforms
COM1
VDD VCL1,VCL2 0 VDD VCL1,VCL2 0 VDD VCL1,VCL2 0 VDD VCL1,VCL2 0 VDD VCL1,VCL2 0 VDD VCL1,VCL2 0 VDD VCL1,VCL2 0 VDD VCL1,VCL2 0 VDD VCL1,VCL2 0 VDD VCL1,VCL2 0 VDD VCL1,VCL2 0
COM2
COM3
SEG1 ~ SEG42 "Off" at COM1 ~ COM3 SEG1 ~ SEG42 "On" at COM1 ~ COM3 SEG1 ~ SEG42 "On" at COM1 only SEG1 ~ SEG42 "On" at COM2 only SEG1 ~ SEG42 "On" at COM3 only SEG1 ~ SEG42 "On" at COM1 and COM2 SEG1 ~ SEG42 "On" at COM1 and COM3 SEG1 ~ SEG42 "On" at COM2 and COM3
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Preliminary
HL14203
2) 1/3 Duty 1/3 Bias Waveforms
VDD VCL1 VCL2 0 VDD VCL1 VCL2 0 VDD VCL1 VCL2 0 VDD VCL1 VCL2 0 VDD VCL1 VCL2 0 VDD VCL1 VCL2 0 VDD VCL1 VCL2 0 VDD VCL1 VCL2 0 VDD VCL1 VCL2 0 VDD VCL1 VCL2 0 VDD VCL1 VCL2 0
COM1
COM2
COM3
SEG1 ~ SEG42 "Off" at COM1 ~ COM3
SEG1 ~ SEG42 "On" at COM1 ~ COM3
SEG1 ~ SEG42 "On" at COM1 only
SEG1 ~ SEG42 "On" at COM2 only SEG1 ~ SEG42 "On" at COM3 only
SEG1 ~ SEG42 "On" at COM1 and COM2
SEG1 ~ SEG42 "On" at COM1 and COM3
SEG1 ~ SEG42 "On" at COM2 and COM3
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Preliminary
HL14203
10. Power On Reset 1) Supply Voltage Detection ( SVD ) The SVD generates an output signal and resets the system when power is first applied and when the voltage drops, I.e.,when the power supply voltage is less than or equal to the power down detection voltage, which is 2.5V, typical. To assure that this function operates reliably, a capacitor must be added to the power supply voltage Vdd rise time when power is first applied and the power supply voltage Vdd fall time when the voltage drops are both at least 1ms. 2) System Reset If at least 1ms is assured as the supply voltage Vdd rise time when power is applied, a system reset will be applied by the SVD output signal when the supply voltage is brought up. If at least 1ms is assured as the supply voltage Vdd fall time when power drops, a system reset will be applied in the same manner by the SVD output signal when the supply voltage is lowered.
VDD
SVD SVD
t1
CE
Display and control data transfer
t2
Internal data
Undefined
Defined
System reset period
Power supply voltage Vdd rise time : t1 > 1ms Power supply voltage Vdd fall time : t2 > 1ms
3) Internal block states during the reset period * Clock generator Reset is applied and the base clock is stopped and OSC pin state is low. * Common , segment drive and display data Reset is applied and the display is turned off but display data is not cleared. * Key scan Reset is applied and all the key data is set to low.
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Preliminary
HL14203
4) Output pin states during the reset period * SEG1/P1 to SEG4/P4 : Low *) * SEG5 to SEG40 : Low * COM1 to COM3 : Low * KS1/SEG41, KS2/SEG42 : Low *) * KS3 to KS5 : X * KS6 : High * SO : High
*) These output pins are forcibly set to the segment output function and held low.
11. Power Down Mode Sleep mode is set up by setting S0 or S1 in the control data to 1. The segment outputs will all go low and the common outputs will also go low, and the oscillator on the OSC pin will stop ( it will be started by a key press). This reduces power dissipation. This mode is cleared by sending control data with both S0 and S1 set to 0. Note that the SEG1/P1 to SEG4/P4 outputs can be used as general purpose output ports according to the state of the P0 and P1 control data bits, even in sleep mode.
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Preliminary
HL14203
12. Oscillator Port
OSC Pin Diagram
R
OSC
Internal clock
SLEEP
C
Oscillator circuit consists of internal R and C.
No Capacitor
Using Capacitor
OSC Open
OSC C
HL14203 has internal resistor and capacitor, so it can be oscillation without external capacitor. If you want to adjust the clock period then you can adjust it using external capacitor.
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Preliminary
HL14203
13. Electrical Characteristics
Absolute Maximum Rating at Ta=25 EVss = 0V ,
Parameter Maximum supply voltage Input voltage Output voltage Symbol VDD max Vin1 Vin2 Vout1 Vout2 Iout1 Iout2 Iout3 Iout4 Pd max Topr Tstg Condition VDD CE,SCK,SI OSC,KIN1 to KIN5, TEST,VCL1,2 SO OSC, SEG1 to SEG42, COM1 to COM3, KS1 to KS6, P1 to P4 SEG1 to SEG42 COM1 to COM3 KS1 to KS6 P1 to P4 Ta = 85 E Rating -0.3 to +7.0 -0.3 to +7.0 -0.3 to VDD+0.3 -0.3 to +7.0 -0.3 to VDD+0.3 300 3 1 5 200 -40 to +85 -55 to +125 unit V V V V V uA mA mA mA mW
Output current Allowable power dissipation Operating temperature Storage temperature
E E
Recommend operating ranges at Ta= -40 E +85 EVss = 0V to ,
Parameter Supply voltage Input voltage Input high level voltage Input low level voltage Recommended external capacitance Guaranteed oscillation range Data setup time Data hold time CE wait time CE setup time CE hold time High level clock pulse width Low level clock pulse width Rise time Fall time SO output delay time SO rise time Symbol VDD VCL1 VCL2 VIH1 VIH2 VIL COSC fOSC tds tdh tcp tcs tch t0H toL tr tf tdc tdr Condition VDD VCL1 VCL2 CE,SCK,SI KIN1 to KIN5 CE,SCK,SI,KIN1 to KIN5 OSC OSC SCK,SI SCK,SI CE,SCK CE,SCK CE,SCK SCK SCK CE,SCK,SI CE,SCK,SI SO,RPU = 4.7k, CL = 10pF*1 SO,RPU = 4.7k, CL = 10pF*1 TBD 160 160 160 160 160 160 160 max 6.0 2/3VDD VDD 1/3VDD VDD 0.8VDD 6.0 0.6VDD VDD 0 0.2VDD TBD 38 TBD min 4.5 typ unit V V V V V V pF KHz ns ns ns ns ns ns ns ns ns s s
160 160 1.5 1.5
Note : *1.Since SO is an open-drain output, these values depend on the resistance of the pull-up resistor RPU and load capacitance CL .
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Preliminary
HL14203
Electrical Characteristics for the Allowable Operating Ranges
Parameter Hysteresis Supply voltage detection Input high level current Input low level current Input floating voltage Pull-down resistance Output off leakage current Output high level voltage Symbol VH SVD IIH IIL VIF RPD IOFFH VOH1 VOH2 VOH3 VOH4 VOL1 VOL2 VOL3 VOL4 VOL5 VMID1 VMID2 Output middle level voltage*2 VMID3 VMID4 VMID5 Oscillator frequency fOSC IDD1 IDD2 IDD3 Condition CE,SCK,SI CE,SCK,SI : V1 = 6.0V CE,SCK,SI : V1 = 0V KIN1 to KIN5 KIN1 to KIN5 : VDD = 5.0V SO : VO = 6.0V KS1 to KS6 : I0 = -500A P1 to P4 : I0 = -1mA SEG1 to SEG42 : I0 = -20A COM1 to COM3 : I0= -100A KS1 to KS6 : I0 = 25A P1 to P4 : I0 = 1mA SEG1 to SEG42 : I0 = 20A COM1 to COM3 : I0 = 100A SO : I0 = 1 mA COM to COM3 : 1/2 bias, Io = 3/4 00A 1 SEG1 to SEG42 : 1/3 bias, Io = 3/4 0A 2 SEG1 to SEG42 : 1/3 bias, Io = 3/4 0A 2 COM to COM3 : 1/3 bias, Io = 3/4 00A 1 COM to COM3 : 1/3 bias, Io = 3/4 00A 1 OSC : C = TBD Sleep mode VDD = 6.0V, output open, 1/2 bias,fOSC = 38 KHz VDD = 6.0V, output open, 1/3 bias,fOSC = 38 KHz min TBD -5.0 0.05VDD 250 6.0 VDD -1.2 VDD -0.5 VDD -0.2 VDD -1.0 VDD -1.0 VDD -1.0 0.2 0.5 1.5 1.0 1.0 1.0 0.1 0.5 1/2 VDD 1/2VDD -1.0 +1.0 2/3VDD 2/3VDD -1.0 +1.0 1/3VDD 1/3VDD -1.0 +1.0 2/3VDD 2/3VDD -1.0 +1.0 1/3VDD 1/3VDD -1.0 +1.0 TBD 38 TBD 100 50 100 350 300 700 600 typ O.1VDD 2.5 max TBD 5.0 unit V V A A V k A V V V V V V V V V V V V V V KHz A A A
Output low level voltage
Current drain
Note : *2. Excluding the bias voltage generation divider resistor built into VCL1 and VCL2
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Preliminary
HL14203
Timing diagram of SIO
CE t0H t0L
SCK tr tf
SI
tds
tdh
SO
VIH1 CE VIL
SCK tcp tcs tch
SI
SO
tdc
tdr
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Preliminary
HL14203
14. Application
1/2 bias ( for use with normal panels )
(p 1) (p 2) (p 3) (p 4) (general-purpose output ports) Used with the backlight controller or other circuit.
OSC +5V *1) VSS TEST VDD COM1 COM2 COM3 P1 / SEG1 P2 / SEG2 P3 / SEG3 P4 / SEG4 SEG5 . . . . . SEG40 S E G 4 1 / K S 1
C 0.047uF VCL1 VCL2 C
. . . . .
From the controller To the controller To the controller power supply
S E G 4 CE 2 SCK K K K K K / I I I I I KKKKK SI SO N N N N N S S S S S 5432165432 *2)
(SEG41) (SEG42)
LCD panel (up to 126 segments
*
Key matrix (up to 30 keys)
*
AE AE
Note : *1). Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is applied and the power supply voltage VDD fall time when power drops are both at least 1 ms, as the HL14203 is reset by the SVD. *2). The SO pin, being an open-drain output, requires a pull-up resistor, Select a resistance (between 1 to 10k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
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Preliminary
HL14203
1/3 bias ( for use with normal panels )
(p 1) (p 2) (p 3) (p 4)
(general-purpose output ports) Used with the backlight controller or other circuit.
OSC +5V *1) VSS TEST VDD COM1 COM2 COM3 P1 / SEG1 P2 / SEG2 P3 / SEG3 P4 / SEG4 SEG5 . . . . . SEG40 S E G 4 1 / K S 1
C 0.047uF C C VCL1 VCL2
. . . . .
From the controller To the controller To the controller power supply
S E G 4 CE 1 SCK K K K K K / I I I I I KKKKK SI SO N N N N N S S S S S 5432165432 *2)
(SEG41) (SEG42)
LCD panel (up to 126 segments
*
Key matrix (up to 30 keys)
*
AE AE
Note : *1). Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is applied and the power supply voltage VDD fall time when power drops are both at least 1 ms, as the HL14203 is reset by the SVD. *2). The SO pin, being an open-drain output, requires a pull-up resistor, Select a resistance (between 1 to 10k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
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Preliminary
HL14203
1/3 bias ( for use with large panels )
(p 1) (p 2) (p 3) (p 4) (general-purpose output ports) Used with the backlight controller or other circuit.
OSC +5V *1) VSS TEST C 0.047uF VDD COM1 COM2 COM3 P1 / SEG1 P2 / SEG2 P3 / SEG3 P4 / SEG4 SEG5 . . . . . SEG40 S E G 4 1 / K S 1
C
C
* R *R
R
VCL1 VCL2
. . . . .
From the controller To the controller To the controller power supply
S E G 4 CE 1 SCK K K K K K / I I I I I KKKKK SI SO N N N N N S S S S S 5432165432 *2)
(SEG41) (SEG42)
LCD panel (up to 126 segments
*
Key matrix (up to 30 keys)
*
AE AE
Note : *1). Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is applied and the power supply voltage VDD fall time when power drops are both at least 1 ms, as the HL14203 is reset by the SVD. *2). The SO pin, being an open-drain output, requires a pull-up resistor, Select a resistance (between 1 to 10k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
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Preliminary

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